The phase locked loop (PLL) method of frequency synthesis is now the most commonly used method of producing high frequency oscillations in modern communications equipment. The principal idea of phase locking is to generate a signal whose phase angle is adaptively tracking variations of the phase angle of a given signal. The complexity of phase locking is due to noise, distortions and frequency variations.
Modern PLL circuits must meet the following set of requirements: operate at high frequency range, have fine frequency resolution, possess low phase noise and reasonable power consumption.
At the picture an example of the 4 GHz sigma-delta PLL chip fabricated in a standard 0,13 um CMOS technology is shown.

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